Race around condition in JK latch and need for flip flops
AN INTERESTING CONDITION IN JK LATCH (FLIP-FLOP) I performed an experiment in the lab to study the behaviour of JK flip flop especially to understand the race around condition in JK flip flop, in which I generated output waveforms with the help of a DSO. In the diagrams below, clock pulse (frequency around 1 Hz) is shown by blue colour and output of JK flip flop in race-around condition (when both the input were High i.e. J=K=1) is shown by red colour. fig.1 fig.2 Here you can see the race between 1 and 0, given that the clock pulse is High. As long as the clock pulse is High, there is multiple toggling between 1 and 0 at the output of JK flip flop. At that moment, when the clock pulse makes a transition from 1 to 0, the output of JK flip flop appears as either 1 or 0. Basically it depends on the previous state (just some nano seconds before the transition). Sometimes it is 1 and sometimes it is 0, so the state (either 0 or 1) which is present ju